1. Field of the Invention
The present invention relates to a testing apparatus and a testing method for RAM (Random Access Memory) within an LSI (Large Scale Integrated) circuit such as a CPU (Central Processing Unit) or a DSP (Digital Signal Processor). In particular the present invention relates to a circuit and a method for acquiring the FBM (Fault Bit Map) information indicating the physical location information (address or bit) of a fault in a fault analysis.
2. Description of the Related Art
In a conventional LSI, such as a CPU or a controller used as the core device of an information processor or a computer system, a primary cache memory may be listed as a RAM comprised in the relevant CPU. A secondary cache memory, such as a large capacity RAM, has been realized with an external SRAM device, such as a CPU, because of limitations on semiconductor technology. Subsequently, with progress of ultra-fine micro-technology in the semiconductor device and improvement of required performance for the CPU, the primary cache memory as well as the secondary cache memory has also been realized. However, as the area in the RAM, which the secondary cache memory gradually occupies, becomes a greater part of the die area of the CPU, reduction in the manufacturing yield due to a failure or a fault caused by dust in the manufacturing processes has become an important problem.
Accordingly, with progress in the ultra-fine micro-technology of the semiconductor device, a new problem has appeared. Namely, the influence on the physical characteristics of the semiconductor of fluctuations in the manufacturing processes has become larger, exceeding the design assumptions, and thereby faults in the semiconductor manufacturing process resulting from insufficient margin in the relevant physical characteristics are being generated more easily than in the past. Moreover, with the relevant problem explained above, the quality of individual RAM will have a large influence on the total quality of LSI and the manufacturing yield thereof.
Accordingly, it is required to improve the circuits in the RAM by conducting fault analysis. Such a fault analysis could be conducted by acquiring the detail information of the relevant fault while a fault caused by insufficient margin in the physical characteristic of the RAM is reproduced.
FIG. 1 illustrates a schematic diagram of an ordinary LSI. Within the LSI 101, an arithmetic logic circuit 141 realizes the inherent function of the relevant LSI and RAMs 121, 131 for holding the data used by the relevant arithmetic logic circuit 141. The arithmetic logic circuit 141 also includes terminals (IN, OUT) for interfacing with external circuits of the LSI. Moreover, the read and write operations of data are conducted between the relevant arithmetic logic circuit 141 and RAMs 121, 131. The RAM includes many elements, such as transistors, in high density among the circuits included in the LSI. Therefore, testing of such a RAM is very difficult.
Therefore, in recent years, many improvements have been made to ensure easier testing of the RAM. One such improvement is by mounting a RAM-BIST (Built-In Self Test) circuit as the self-diagnosis mechanism for RAM into the LSI. The relevant RAM-BIST circuit is formed of a RAM-BIST pattern generating block 111 and fault discriminating circuits 122, 132. In FIG. 1, the RAM-BIST pattern generating block 111 and fault discriminating circuits 122, 132 are objects to which the circuit of the present invention is mounted, while the RAMs 121, 131 are objects in which ease of fault analysis can be improved with the present invention.
FIG. 2 illustrates an example of a structure of a RAM-BIST circuit of the background art. The RAM-BIST circuit in this embodiment is formed of a RAM-BIST pattern-generating block 201. The RAM-BIST circuit also includes a test pattern generating circuit 214 as a peripheral circuit of the test object RAM 221, an expected value comparing circuit 231 forming a fault detecting circuit, and a fault holding FF (flip-flop) 241.
The test pattern generating circuit 214 built in the RAM-BIST pattern generating block 201 sets the instruction code or mode signal to be given to the test pattern generating circuit 214 with a scan FF (flip-flop) group 211 connected to a scan chain, which is input from the scan-in and output to the scan-out. The test pattern generating circuit 214 also sets the initial value of a counter within the test pattern generating circuit 214 with a scan FF group 212 within the test pattern generating circuit 214. The RAM-BIST pattern-generating block 201 generates the programmable signal to a test object RAM 221 and provides the signal to an expected value comparing circuit 231 and a fault holding FF 241 forming a fault discriminating circuit.
The write enable (WE) signal for discriminating the write and read operations, the writing data, and a read or write object address (Addr) are distributed to the test object RAM 221. An expected value data for comparison with the read data from the test object RAM 231, and a negative logic load enable (−LE) signal for determining discrimination or non-discrimination of a fault, are distributed to an expected value comparing circuit 231 which forms the fault discriminating circuit. During the write operation, the relevant expected value data is the “don't care” value, while during the read operation, the write data is the “don't care” value. Therefore, the expected value data signal and the data signal may be used during the write operation in common through the control with the write enable (WE) signal.
The fault holding FF 241 forming the fault discriminating circuit includes a circuit for comparing the read data of the test object RAM 221 with the expected value data. The fault holding FF 241 also includes an FF for recording the relevant comparison result (fault information). In general, one of these circuits is provided for each bit of the RAM output. The expected value data to be read from the output of the test object RAM, and the negative logic load enable (−LE) signal for determining fault discrimination, are received from the RAM-BIST pattern-generating block 201. The fault discrimination should not be conducted during the write operation of the relevant test object RAM because the relevant RAM output is the “don't care” value or a fixed value. Accordingly, during the write operation of the relevant test object RAM, the negative logic load enable (−LE) signal, which is prevented from executing the fault discrimination, is generated by the test pattern generating circuit 214.
Moreover, in the test for mass-production, the RAM-BIST pattern-generating block generates the test pattern signal for each clock cycle and executes the fault discrimination many times while the address of RAM is changed in the single test. If a fault is detected even once among a plurality of fault discriminations, the fault is discriminated in the relevant test object bits. Therefore, a record of faults detected in the past can be held even when a feedback loop circuit exists in the fault discriminating circuit and a fault is not detected during the new fault discriminating period. Moreover, if a further fault is detected after faults have been detected in the past, a record of the fault is over-written by the relevant feedback loop circuit. The fault holding FF forming the fault discriminating circuit is connected to the scan-chain other than the scan-chain of the RAM-BIST pattern-generating block. Accordingly, the fault holding FF can be initialized by clearing the fault information at the time of initial setting before start of the test and the relevant test result can be read from a scan-out 2.
FIG. 3 illustrates an example of a fault discriminating circuit structure for one bit in the background art. The expected value comparing circuit is formed of an Ex-OR (exclusive OR) gate 304. When the read data from the test object RAM is matched with the expected value data, the expected value comparing circuit outputs ‘0’ because the test result is judged good. When the read data is mismatched, the expected value comparing circuit outputs ‘1’ because the test result is judged bad (fault). The relevant test result is written into the FF 306 passing through the OR (logical sum) gate 305.
Moreover, when the feedback loop circuit is used for test (loop=‘1’) and a fault has already been detected in the same bit, the state having detected the relevant fault is held in the FF 306 with the relevant feedback loop formed of the AND (logical product) gate 303. Accordingly, even after the fault discrimination has been repeated a number of times, the FF 306 can be used as a flag indicating whether a fault is generated in the relevant bit or not. Comparison of the expected value should not be conducted during the write operation to the test object RAM because the read data from the relevant test object RAM does not have any meaning. Therefore, the negative load enable (−LE) signal is set to (−LE=‘1’) while the RAM-BIST pattern generating block and updating of the value held by the FF 306 is inhibited with the IH (inhibit) terminal of the FF 306. In general, since one or more cycles are required to read the read data from the RAM, the expected value and negative logic load enable signal are adjusted in the cycle with the cycle adjusting circuits 301, 302 formed of the shift register in order to adjust the cycle of the read data.
FIG. 4 illustrates an example of test flow in which the RAM-BIST circuit of the background art is used. This is an example of a test flow used for fault discrimination of the relevant LSI, or for determining the relief object bits of the fault, using a redundant circuit of RAM in the mass production test of LSI.
First, after start of test (step S401), the instruction code and mode signal are set by scan-in for the scan chain of the RAM-BIST pattern-generating block. The initial value of the counter within the RAM-BIST pattern generating block is also set (step S402). In this case, the feedback loop circuit in the fault discriminating circuit is set to ON (loop=‘1’), and initialization is conducted by clearing the fault information held in the fault holding FF in the fault discriminating circuit (step S403).
As the next step, as many clocks as required for the relevant RAM test are applied to the test object RAM (step S404 to S405). The write and read operations of the test object RAM are executed with the test pattern automatically generated in the RAM-BIST pattern generating block each time a clock is applied. Fault discrimination in the fault discriminating circuit is also conducted. After application of the clocks required for the test object RAM, the fault holding FF in the fault discriminating circuit holds the fault information for each bit. The relevant fault information is read (step S406) to the external side of the test object LSI using the scan chain. Thereafter, the test using the RAM-BIST circuit is completed (step S407). Since the relevant fault information corresponds to each bit of the test object RAM, a fault-generating bit can be discriminated from the bit location in the relevant scan chain. However, it is still impossible to discriminate a fault generating address of the test object RAM.
In a fault analysis of an LSI, it is required to identify the physical location where a fault is generated. Moreover, when the relevant fault is generated, it is required to discriminate whether a high value was read when a low value is expected, or, on the contrary, whether a low value was read when a high value was expected. As a method of fault analysis of LSI, it is also required to estimate a cause of fault of the test object RAM from the information. Such an estimate may include a distribution of the physical locations of the detected faults and a profile of fault generation. Such information is called the FBM (Fault Bit Map) information.
FIG. 5 illustrates an example of the test flow when the FBM information is obtained in the RAM-BIST circuit of the background art. The RAM-BIST circuit in the background art is not provided with a means for identifying the fault generating address. Therefore, the fault information being held in the fault holding FF of the fault discriminating circuit is read with the scan chain whenever the data is read from the test object RAM, whether or not a fault is generated in this timing. A pattern location where a fault is detected can be identified by scan shift of the fault information after each read operation of the test object RAM. The fault generating address and the expected value data obtained with the read operation can be analyzed with the relevant scan-shifted information. Each step of the relevant test flow will be explained below.
First, the instruction code and mode signal are set by conducting scan-in for the scan chain of the RAM-BIST pattern generating block after start of test (step S501). The initial value of the counter in the RAM-BIST pattern-generating block is also set (step S502). In this case, the feedback loop circuit in the fault discriminating circuit is set to OFF (loop=‘0’), and initialization is executed by clearing the fault information held by the fault holding FF within the fault discriminating circuit (step S502).
As the next step, clocks are applied to the test object RAM (steps S503). The write and read operations of the test object RAM are executed with the test pattern automatically generated in the RAM-BIST pattern generating block whenever the clock is applied. Fault discrimination of the relevant test object RAM is conducted with the fault discriminating circuit. After each read operation (step S504) of the test object RAM, the fault information held in the fault holding FF in the fault discriminating circuit is read to the external side of the test object LSI using the scan chain (step S505). With repetition of the process explained above (steps S504 to S505), the test using the RAM-BIST circuit is completed (step S507).
In this example, fault information, such as the content held in the fault holding FF in the fault discriminating circuit, is scan shifted, but the content held in the FF for setting, such as instruction code and mode signal in the pattern generating circuit, is not scan shifted, in order to hold the setting state for continuation of operations with application of the next clock. The read operation by application of the relevant clock and scan shift of the fault information is repeated until the test is completed. In this test flow, a fault generating bit and a fault generating read cycle can be analyzed easily.
High speed operation test of the test object RAM is possible in the test flow of FIG. 4, since a test process is completed only with application of clock after the initial setting. However, since the bit information amount of one bit is provided in the address direction for each bit of the output of test object RAM, a problem arises in that the information of the fault generating address cannot be obtained and thereby the FBM information cannot be attained.
Moreover, the FBM information can be acquired in the test flow of FIG. 5, but the read operation by scan shift of the fault holding FF in the fault discriminating circuit is generated for each read operation of the test object RAM. Therefore, as a single clock is applied during operation of the test object RAM, a fault of the type to be generated by high-speed continuous application of the clock to the RAM cannot be reproduced in some cases.
Therefore, the test method using the RAM-BIST circuit of the background art cannot be said to have higher fault analysis capability, because it is impossible to simultaneously realize operation speed similar to the actual operating condition of the test object LSI and acquire test and FBM information based on the operation pattern.
FIG. 14 illustrates an example of structure of an ordinary RAM cell circuit of one bit. FIG. 14 illustrates the RAM cell circuit of one bit formed of pMOS transistors (positive Metal Oxide Silicon) 1401, 1402, nMOS transistors (negative Metal Oxide Silicon) 1403,1404, and INV (inverter) gates 1405, 1406.
Next, the write operation in the relevant RAM cell circuit will be explained. First, the bit lines BL1409, XBL1410 are precharged in the initial state. Next, when the address, write data, and write enable signal (not illustrated) reach the RAM input terminal, and the clock pulse is also applied, the RAM starts operation and the BL1409 and XBL1410 are driven in accordance with the write data. Next, when the row address (not illustrated) is decoded, the INV (inverter) gates 1405, 1406 forming a recording element become conductive, and the data is held in the relevant storage element as the storage state Q by generating the pulse to the decoded word line WL1408. Moreover, the precharge operation is started with a PC14070 and thereby the bit lines BL1409 and XBL1410 are driven to the high state.
The read operation of the relevant RAM cell circuit will now be explained. First, the bit lines BL1409, XBL1410 are precharged in the initial state. Next, when the address, write data, and write enable signal (not illustrated) reach the RAM input terminal and the clock pulse is applied, the RAM starts operation. Next, when the row address (not illustrated) is decoded, the INV (inverter) gates 1405,1406, which form a recording element, become conductive by generating the pulse in the decoded word line WL1408. With content of the storage state Q of the relevant storage element, potential of the bit lines BL1409 or XBL1410 is lowered and a potential difference is generated between the bit lines BL1409 and XBL1410. Here a sense amplifier (not illustrated) starts operation and a read value is determined by a potential difference between the bit lines BL1409 and XBL1410. Moreover, the PC1407 starts the precharge operation to drive the bit lines BL1409, XBL1410 to the high state.
FIG. 15 illustrates a timing chart showing an example of a fault of the type generated by high-speed application of a continuous clock to the RAM, namely an example of a fault generated in the high-speed operation test of RAM.
For example, a fault may be generated because the operation of the next cycle is started before completion of the precharge of the bit line. In particular, if the read operation starts potential fall 1502 before sufficient completion of potential rise by the precharge 1501, a potential difference between the bit lines BL and XBL may not be sufficient, and erroneous data may be output. Otherwise, the time (delay time) required to establish an output in the read operation is increased, adversely effecting the performance.
Moreover, when a delay time becomes longer because a sufficient potential difference between the bit lines BL and XBL cannot be acquired, a word line pulse 1504 is sometimes generated before completion 1503 of the decoding of the address. When the output delay becomes large in such a read operation, an increment of the relevant delay can be detected with an earlier application of the clock after the read operation.
Moreover, a precharge sometimes produces an adverse effect on the storage element. When the assert period overlaps with the precharge period of the word line, an adverse effect may be produced in the holding capability of the storage element. This adverse affect may be due to the before and after relationship of the timings of the generation of word line pulse 1504 by the decoding and the precharge 1505, because both bit lines BL and XBL of the storage element are driven to the high value. Even when the relevant adverse effect is within the range of margin of the RAM characteristic, however, the data cannot be held normally in some cases if such adverse effect is generated repetitively at a high rate for the RAM cell exhibiting the bad characteristic. Moreover, if an interval of the relevant word line pulse 1504 is sufficiently long, there arises a problem in that there is a higher possibility that a fault cannot be detected, because the potential is recovered with the loop circuit of the inverter which forms a storage element.
FIG. 16 illustrates a timing chart for a read operation of the next cycle, which is started before sufficient precharge of the bit lines during the write operation in the high-speed operation test of RAM.
Access may also be made to the other addresses during the write and read operations, and the data values of the relevant write object and read object will be in an inverted relationship with each other. If the next read operation starts before completion of precharge, sufficient potential difference is not generated in some cases between the bit lines BL and XBL. This may be because the precharge start timing is delayed, or the precharge driving capability is low, or when the sense amplifier operation starts due to a complicated reason such as drive capability of RAM cell is low. In this case, an error is generated in the read data, but a sufficient precharge is generated when the read cycle is longer. Accordingly, there arises a problem that the fault cannot be reproduced.
The JP-A No. 1999-39226 discloses in a test object RAM and a self-test circuit for testing the test object RAM. The self-test circuit comprises a controller for outputting a control signal when it receives the test clock and the test start signal. An address generator generates an address signal when it receives the control signal and outputting such address signal to the RAM.
A data generator generates a test data when it receives the control signal and outputs the test data to the RAM. A comparator compares the given test data output by the data generator to the actual data read after the RAM and writes the given test data and outputs an error signal when the test data is different from the actual data. A scan circuit receives the actual data output from the storage device or the address signal output from the address generator and provides a serial output.
A multiplexer selectively outputs, on the basis of the control signal, any error signal output from the comparator, an error signal output from the scan circuit, or an actual data output from the scan circuit or the address signal When the error signal is output after start of the test, the actual data when the error was generated is output to the external side via the multiplexer, and moreover the address signal corresponding to such actual data is output to the external side via the multiplexer.
Namely, this technology discloses that when an error is generated in the RAM test, the actual data or address related to the error generated is held and the relevant information is read to the external side of the LSI with the scan shift.
However, the technology disclosed by the JP-A No. 1999-39226 has a problem in that since the test operation of RAM is stopped when a fault in the test object RAM is detected, a fault of the type generated when the clocks are continuously applied in a higher rate to the relevant RAM cannot be reproduced.